Process for fabricating semiconductor device and method for generating mask pattern data

ABSTRACT

A method of fabricating a semiconductor device including a first wiring pattern extending in a vertical direction and a second wiring pattern identical in geometry to the first wiring pattern and extending in a (horizontal) direction orthogonal to the vertical direction, including the steps of: employing linearly polarized illumination to perform exposure along a mask pattern including mask patterns used to form the first and second wiring patterns, respectively; and subsequently forming the first and second wiring patterns having a geometry along the mask patterns. The mask patterns to form the first and second wiring patterns are formed to be different in geometry.

TECHNICAL FIELD

The present invention relates to semiconductor device fabricationmethods and mask pattern data generation methods and particularly tosuch methods employing lithography using linearly polarized light.

BACKGROUND ART

In fabricating a semiconductor integrated circuit device a fine patternis transferred on a semiconductor wafer by lithography. In lithography aprojection exposure apparatus is typically used and a pattern of aphotomask attached on the apparatus is transferred onto thesemiconductor wafer to form a pattern of a device.

In recent years there has been a demand for highly integrated devicesand the devices' increased speed of operation and in order to meet thedemand finer patterns are pursued. Under such circumstance, exposureapparatuses have conventionally been used with a numerical aperture (NA)increased to provide increased resolution.

Furthermore, as a method improving an effective NA a method of exposurereferred to as immersion lithography has also been considered. Inimmersion lithography exposure, a space between a lens and a plane ofphotoresist serving as a sample to be printed is filled with liquid toincrease the space's index of refraction to provide improved effectiveNA. (As seen from a different point of view, exposure is done with lighthaving a reduced effective wavelength.) A technique associated withimmersion lithography is described for example in non-patent Document 1indicated hereinafter.

Thus there is an increasing demand for increased effective numericalaperture to provide patterns improved in contrast (or resolution).Currently, an apparatus with an NA of 0.9 or higher has been produced asa prototype. Furthermore, an exposure apparatus has also been planedthat is combined with immersion lithography to provide an NA asconverted of approximately 1.3. It is known that when such an extremelyhigh numerical aperture exposure apparatus is used a pattern transferredsignificantly varies in contrast depending on the direction ofpolarization of light employed for exposure.

In general it is known that when polarized light along a direction inwhich a pattern extends (hereinafter also referred to as S polarizedlight) is used to provide exposure, a high contrast is obtained. Whennon-polarized light is used to provide exposure, resolution is reduced.When polarized light perpendicular to the direction in which the patternextends (hereinafter also referred to as P polarized light) is used toprovide exposure, further decreased resolution is provided. This isdescribed for example in Japanese Patent Laying-Open Nos. 6-275493(Conventional Example 1), 5-90128 (Conventional Example 2), and 6-140306(Conventional Example 3).

Patent Document 1: Japanese Patent Laying-Open No. 6-275493

Patent Document 2: Japanese Patent Laying-Open No. 5-90128

Patent Document 3: Japanese Patent Laying-Open No. 6-140306

Non-Patent Document 1: “Immersion Lithography Technology”, [on line],NIKON corp. [retrieved Feb. 19, 2004], Internet<URL:http://www.nikon.co.jp/main/jpn/profile/technology/immersion/>.

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

Such semiconductor device fabrication method as described above,however, has a disadvantage as follows:

As has been described above, the direction of polarization of light forexposure affects the contrast of a pattern formed. As adapting immersionlithography or the like provides improved numerical aperture (NA),exposure's polarization dependency further increases. Consequently, thedirection of polarization of light for exposure affects the pattern ingeometry and the like and the pattern's geometry as desired may notreliably be obtained.

In contrast, Conventional Examples 1 and 2 disclose a method of exposurefor a pattern extending only in one direction. Furthermore, ConventionalExample 3 discloses a method of exposure that separately forms mask forforming orthogonal, bi-directional pattern. The example, however, failsto disclose the concept that a dimension is corrected by an amountvaried for different directions of the pattern. The present invention isthus distinguished in precondition and configuration from ConventionalExamples 1-3.

The present invention has been made to overcome the aforementioneddisadvantages and it contemplates a semiconductor device fabricationmethod and mask pattern data generation method capable of stabilizing ingeometry a pattern formed on a wafer.

Means for Solving the Problems

The present semiconductor device fabrication method is a method offabricating a semiconductor device having a first pattern extending in afirst direction and a second pattern identical in geometry to the firstpattern and extending in a second direction orthogonal to the firstdirection, and includes the steps of: employing linearly polarizedillumination to perform exposure along a mask pattern including a firstand second mask patterns used to form the first pattern and the secondpattern, respectively; and subsequently forming the first and secondpatterns having a geometry along the mask pattern, the first and secondmask patterns being different in geometry.

The present mask pattern data generation method is a method ofgenerating mask pattern data defining a mask pattern for forming apattern on a wafer by linearly polarized light, the method introducing adimensional correction in an amount varied between a first directionparallel to the linearly polarized light's direction of polarization anda second direction orthogonal to the first direction.

EFFECTS OF THE INVENTION

The present invention can stabilize in geometry a pattern formed on awafer through exposure.

The foregoing and other objects, features, aspects and advantages of thepresent invention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view schematically showing a configuration of asemiconductor device of the present invention in a first embodiment.

FIG. 2 is a top view of a layout of a pattern in the FIG. 1semiconductor memory device at a memorymat portion.

FIG. 3A is a top view of a layout of a gate wiring pattern of aperipheral circuitry portion of the present semiconductor device in thefirst embodiment, showing a vertical gate pattern.

FIG. 3B is a top view of a layout of a gate wiring pattern of aperipheral circuitry portion of the present semiconductor device in thefirst embodiment, showing a horizontal gate pattern.

FIG. 4A is a top view of a mask pattern used to form the FIG. 3A wiringpattern.

FIG. 4B is a top view of a mask pattern used to form the FIG. 3B wiringpattern.

FIG. 5A is a top view of a mask pattern used to form a dense wiringpattern of the peripheral circuitry portion of the present semiconductordevice in the first embodiment, showing a vertical mask pattern forforming a vertical dense pattern.

FIG. 5B is a top view of a mask pattern used to form a dense wiringpattern of the peripheral circuitry portion of the present semiconductordevice in the first embodiment, showing a horizontal mask pattern forforming a horizontal dense pattern.

FIG. 6A is a top view of a mask pattern used to form an L-shaped wiringpattern, showing a typical layout of the mask pattern.

FIG. 6B is a top view of a mask pattern used to form an L-shaped wiringpattern, showing a typical layout of the mask pattern.

FIG. 6C is a top view of a mask pattern used to form an L-shaped wiringpattern, showing a layout of a mask pattern used in a method offabricating the present semiconductor device in the first embodiment.

FIG. 6D is a top view of a mask pattern used to form an L-shaped wiringpattern, showing a layout of a mask pattern used in a method offabricating the present semiconductor device in the first embodiment.

FIG. 7A is a top view of a mask pattern used to form a straight-jointwiring pattern in the present semiconductor device of the firstembodiment, showing a vertical mask pattern for forming a verticalmatched wiring pattern.

FIG. 7B is a top view of a mask pattern used to form a straight-jointwiring pattern in the present semiconductor device of the firstembodiment, showing a horizontal mask pattern for forming a horizontalmatched wiring pattern.

FIG. 8A is a top view of one example of a mask pattern used to form awiring pattern in the present semiconductor device of a secondembodiment, showing a vertical mask pattern for forming a verticalwiring pattern.

FIG. 8B is a top view of one example of a mask pattern used to form awiring pattern in the present semiconductor device of the secondembodiment, showing a horizontal mask pattern for forming a horizontalwiring pattern.

FIG. 9A is a top view of another example of a mask pattern used to forma wiring pattern in the present semiconductor device of the secondembodiment, showing a vertical mask pattern for forming a verticalwiring pattern.

FIG. 9B is a top view of another example of a mask pattern used to forma wiring pattern in the present semiconductor device of the secondembodiment, showing a horizontal mask pattern for forming a horizontalwiring pattern.

FIG. 10A is a top view of a mask pattern employed to form a holepattern, showing a typical mask pattern.

FIG. 10B is a top view of a mask pattern employed to form a holepattern, showing a layout of the mask pattern that is employed in amethod of fabricating a semiconductor device in a third embodiment ofthe present invention.

FIG. 11A is a top view of the FIG. 10A mask patterns in a set.

FIG. 11B is a top view of the FIG. 10B mask patterns in a set.

FIG. 12A is a top view showing a result of transferring a pattern byusing the FIG. 11A mask patterns.

FIG. 12B is a top view showing a result of transferring a pattern byusing the FIG. 11B mask patterns.

FIG. 13A is a cross section of a resist pattern after a mask pattern istransferred in the present semiconductor fabrication method in a fourthembodiment.

FIG. 13B is a cross section of a resist pattern after a mask pattern istransferred in the present semiconductor fabrication method in thefourth embodiment.

FIG. 13C is a cross section of a resist pattern after a mask pattern istransferred in the present semiconductor fabrication method in thefourth embodiment.

FIG. 13D is a cross section of a resist pattern after a mask pattern istransferred in the present semiconductor fabrication method in thefourth embodiment.

FIG. 14A is a top view of a resist pattern after a mask pattern istransferred in the present semiconductor fabrication method in thefourth embodiment.

FIG. 14B is a top view of a resist pattern after a mask pattern istransferred in the present semiconductor fabrication method in thefourth embodiment.

FIG. 15 shows one example of a configuration of a semiconductorfabrication apparatus.

FIG. 16 shows one example of a flowchart of the present mask patterndata generation method in the first embodiment.

FIG. 17 shows another example of the flowchart of the present maskpattern data generation method in the first embodiment.

FIG. 18 shows a first step in a typical wiring pattern formationprocess.

FIG. 19 shows a second step in the typical wiring pattern formationprocess.

FIG. 20 shows a third step in the typical wiring pattern formationprocess.

FIG. 21 illustrates a flowchart of the typical wiring pattern formationprocess.

DESCRIPTION OF THE REFERENCE SIGNS

1: source of light, 2: mirror, 3: fly eye lens, 4: polarizing plate, 5:mask pattern, 6: fine pattern, 7: photomask, 8: objective lens, 9:wafer, 10: memorymat portion, 11: peripheral circuitry portion, 12:drawn-line portion, 13: line and space pattern, 14, 15: wiring pattern,16, 17: mask pattern, 18: mask pattern (dimension uncorrected), 19, 20:mask pattern, 21 mask pattern (dimension uncorrected), 22: main pattern(horizontal direction), 23: hammer head (horizontal direction), 24: mainpattern (vertical direction), 25: hammer head (vertical direction), 26,26A: main pattern, 27: subpattern, 28: main pattern (vertical direction)29: subpattern (vertical direction), 30: main pattern (horizontaldirection), 31: subpattern (horizontal direction), 32, 40: halftonefield portion, 33, 34: opening, 41, 42: opening, 43: photoresist, 44,45: hole, 46: abnormally transferred pattern, 50: substrate, 51, 51A,52, 52A: resist pattern, 101, 102: designed pattern, 103, 104: maskpattern, 105, 106: main portion, 107, 108: projection, 109, 110: innerserif portion (recess), 111, 112: serif portion (protrusion), 113, 114:mask pattern, 113A, 114A: corner, 115A, 115B: main portion, 116A, 116B:projection, 117A, 117B, inner serif portion, 118A, 118B: serif portion,120: wafer, 121: insulation layer, 121A, insulation film, 122:conductive layer, 122A: wiring pattern, 123: resist film, 123A: resistpattern.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter the present semiconductor device fabrication and maskpattern data generation methods will be described in embodiments withreference to FIGS. 1-21.

First Embodiment

FIG. 1 is a top view of a semiconductor device of the present inventionin a first embodiment.

As provided in the present embodiment the semiconductor device is flashmemory, one example of non-volatile semiconductor memory device. Notethat while in the present embodiment the present invention is describedas being applied by way of example to the above flash memory, thepresent invention is not limited thereto and is applicable to anysemiconductor device.

With reference to FIG. 1, the flash memory (or semiconductor device)includes a memorymat portion 10 and a peripheral circuitry portion 11.

FIG. 2 shows one example of a gate wiring pattern of memorymat portion10.

With reference to FIG. 2, the gate wiring pattern includes a line andspace pattern 13 formed on a memory cell and a drawn line portion 12connected to a contact pad.

Line and space pattern 13 is the densest fine pattern in the flashmemory. Note that line and space pattern 13 occupies approximately morethan 50% of the entirety of the area of the chip, and reducing line andspace pattern 13 in pitch can effectively provide an efficiently reducedchip area (i.e., the chip shrink effect).

Accordingly, linearly polarized light polarized in a direction parallelto that in which line and space pattern 13 extends (linearly polarizedlight that will be S polarized light for line and space pattern 13), isemployed to perform an exposure process. Thus line and space pattern 13can be increased in resolution and reduced in pitch.

The aforementioned linear polarization light can be obtained byemploying linearly polarized illumination. FIG. 15 shows one example ofa semiconductor fabrication apparatus including linearly polarizedillumination that implements the semiconductor device fabrication methodin accordance with the present embodiment.

With reference to FIG. 15, a source of light 1 has a back side facing amirror 2. The source of light 1 emits light which passes through a flyeye lens 3 to be uniformed and then passes through a polarizing plate 4to provide linearly polarized light polarizing in a prescribeddirection. In the present embodiment, linearly polarized light (Spolarized light), polarized along a fine pattern 6 (e.g., line and spacepattern 13) on a wafer 9 and a mask pattern 5 employed to form pattern6, is generated.

The linearly polarized light provided by polarizing plate 4 arrives at aphotomask 7 having mask pattern 5. The linearly polarized light passesthrough photomask 7, and further passes through an objective lens 8 (aprojection lens) and arrives at wafer 9. Thus mask pattern 5 istransferred on a resist film deposited on wafer 9.

The FIG. 15 exposure apparatus employs light having a wavelength of 193nm and a lens with an NA of 0.92 to perform exposure in the atmosphere.It should be noted however that these conditions are exemplary, and forexample improving the len's NA and employing immersion lithography toform pattern 6 further reduced in pitch, is of course allowed for. Forexample, F2 excimer laser can be used to provide exposure to lighthaving a wavelength of 157 nm. Note that if the source of light 1 is anexcimer laser, it emits already linearly polarized light. In that case,a λ/4 plate can simply be used to rotate a plane of polarization 90° toswitch between S polarization and P polarization.

A typical process for forming a wiring pattern on a wafer will bedescribed with reference to FIGS. 18-21.

With reference to FIG. 18, a wafer 120 with an insulation layer 121 anda conductive layer 122 deposited thereon further has a resist film 123deposited thereon (in FIG. 21 at step 130).

A mask pattern is then used for exposure (in FIG. 21 at step 131).Subsequently a development process is performed to form a resist pattern123A corresponding to the mask pattern, as shown in FIG. 19.

The intermediate product is etched with resist pattern 123A serving as amask to form a wiring pattern 122A on wafer 120 with an insulation film121A interposed therebetween. Subsequently, resist pattern 123A isremoved (in FIG. 21 at step 132).

Description will now be made for a method of generating mask patterndata of a photomask employed in the above described exposure process.

Generally, in forming a mask pattern, an amount of variation of the maskpattern that is introduced when it is transferred to a wafer (i.e., anamount of variation of the pattern) is previously considered and themask pattern having the variation corrected is formed. This approach isreferred to as optimal proximity correction (OPC). In this approach adimension that is corrected will be referred to as an amount ofcorrection in dimension.

If exposure is performed with unpolarized (randomly polarized) light,there is not introduced a dimensional correction varied in amountbetween vertical and horizontal directions. If exposure is performedwith linearly polarized light to form a pattern, however, the patternvaries in resolution between vertical and horizontal directions. Assuch, if identically dimensioned mask patterns are used to formvertically and horizontally extending patterns, the patterns would havedifferent dimensions in vertical and horizontal directions.

In contrast, the present embodiment provides a mask pattern datageneration method introducing a dimensional correction varied in amountbetween a vertical direction (a first direction) parallel to a directionof polarization of linearly polarized light used to perform exposure anda horizontal direction (a second direction) orthogonal to the verticaldirection.

This allows a pattern steady in geometry to be obtained regardless ofthe direction of polarization of light used for exposure.

FIG. 16 shows a procedure of the mask pattern data generation method inaccordance with the present embodiment.

With reference to the figure, data of a pattern to be formed on a wafer(“data of a designed pattern”), data of a direction of polarization oflinearly polarized light used for exposure (“data of a direction ofpolarization”), other conditions for exposure (numerical aperture (NA),illumination's coherence (a), and information of resist (resist anddevelopment parameter) are input (in FIG. 16 at step 61).

When the data of the designed pattern, the data of the direction ofpolarization, and the conditions for exposure are used to calculate anoptical image (in FIG. 16 at step 62). Herein, a relationship betweenthe direction of polarization and that of individual designed pattern isreferenced.

The calculated optical image and the above described resist (anddevelopment) parameter are used to calculate an image transferred (inFIG. 16 at step 63).

From the image transferred, data of a mask pattern formed on a photomaskis obtained (in FIG. 16 at step 64) and calculated mask pattern data isoutput (in FIG. 16 at step 65).

FIG. 17 shows the FIG. 16 mask pattern data generation method'sprocedure in an exemplary variation.

With reference to FIG. 17, in this exemplary variation the finestpattern (a dense fine pattern) in input data of designed patterns isautomatically extracted (in FIG. 17 at step 61A) and therefrom adirection of polarization of linearly polarized light used for exposureis defined (in FIG. 17 at step 61B). Thus the above described data of adirection of polarization is automatically obtained, which can eliminatethe necessity of entering the data.

Herein the direction of polarization of linearly polarized light isdefined as a direction parallel to that in which the dense fine patternextends. This allows the finest designed pattern to be transferred byusing linearly polarized light that serves as S polarized light for thepattern. As a result, the dense fine pattern can be improved inresolution and an effectively reduced chip area can thus be achieved.

Note that in the above described mask pattern data generation methodallows for creating an electric design automation (ETA) program thatimplements steps 61-65.

The above described mask pattern data generation method provides a maskpattern and its effect, as will be described hereinafter.

FIGS. 3A and 3B show one example of a gate wiring pattern in theabove-described flash memory (semiconductor device) at peripheralcircuitry portion 11. Note that the FIGS. 3A and 3B patterns areidentical. More specifically, the FIG. 3A pattern rotated by 90°corresponds to the FIG. 3B pattern.

With reference to FIGS. 3A and 3B, peripheral circuitry portion 11 isprovided with wiring patterns 14, 15 wider in pitch than line and spacepattern 13 in memorymat portion 10 aforementioned. More specifically,for example, line and space pattern 13 has a width of approximately 60nm and a pitch of approximately 120 nm, whereas wiring patterns 14, 15have a pitch of approximately 240 nm at the narrowest portion.

Wiring pattern 14 (a first pattern) extends in a vertical direction (afirst direction) and wiring pattern 15 (a second pattern) extends in ahorizontal direction (a second direction). Wiring patterns 14, 15 areequal in width (WO).

Line and space pattern 13 and wiring patterns 14, 15 are formed throughan identical exposure process using identical linearly polarized light.The linearly polarized light used to perform exposure has a direction ofpolarization defined to be parallel to that in which line and spacepattern 13 extends. Consequently, the direction of polarization isparallel to that in which wiring pattern 14 extends (in FIGS. 3A and 3B,the vertical direction). In other words, the linearly polarized lightserves as S polarized (transverse electric (TE) wave) light for wiringpattern 14 and P polarized (or transverse magnetic (TM) wave) light forwiring pattern 15.

As has been described above, a pattern transferred by S polarized lightis higher in resolution than that transferred by P polarized light. Assuch, when geometrically identical mask patterns are used to providewiring patterns 14 and 15, they have a dimensional difference ofapproximately 3 nm.

FIGS. 4A and 4B show mask patterns 16, 17 used to form the FIGS. 3A and3B wiring patterns 14, 15.

With reference to FIGS. 4A and 4B, wiring pattern 14 formed by Spolarized light corresponds to mask pattern 16 (a first mask pattern),which has a width (W1), and wiring pattern 15 formed by P polarizedlight corresponds to mask pattern 17 (a second mask pattern), which hasa width (W2) smaller than width W1. Note that in FIG. 4A a patterngeometrically identical to mask pattern 17 is drawn inside mask pattern16 as a mask pattern 18 by a broken line. In FIG. 4A mask patterns 16and 18 provide a horizontal dimensional difference of 16 nm and novertical dimensional difference.

As has been described previously, wiring pattern 14 formed by Spolarized light is higher in resolution than wiring pattern 15 formed byP polarized light, and if wiring patterns 14 and 15 are formed throughgeometrically identical mask patterns, wiring pattern 14 has a widthsmaller than wiring pattern 15. This can be addressed by correcting themask pattern in dimension, as described above, to increase wiringpattern 14 in width and as a result allow wiring patterns 14 and 15formed on a wafer to be equal in width (WO).

Note that wiring patterns 14 and 15 is larger in pitch than line andspace pattern 13, and wiring pattern 15 formed by P polarized light isalso sufficiently be resolved. Furthermore, wiring pattern 14 is formedby S polarized light and relatively has a margin for example in depth offocus (DOF), and if mask pattern 16 is increased to be larger in widththan mask pattern 17 wiring pattern 14 is still sufficiently beresolved.

As an amount of correction in dimension of a mask pattern is variedaccording to a relationship between a direction in which a wiringpattern extends and that of polarization, in the memorymat portion afinely pitched gate writing pattern can be formed while in theperipheral circuitry portion a gate pattern can be formed free of adifference in dimension between vertical (first) and horizontal (second)directions and hence as designed.

In a concept similar to the above a dimensionally corrected mask patternin another example will be described.

FIGS. 5A and 5B show mask patterns 19, 20 used to form a dense patternin the above described flash memory at the peripheral circuitry portion.

With reference to the figures, a wiring pattern formed by S polarizedlight corresponds to mask pattern 19 (a first mask pattern), which has awidth (W1), and a wiring pattern formed by P polarized light correspondsto mask pattern 20 (a second mask pattern), which has a width (W2)smaller than width W1. Note that in FIG. 5A a pattern geometricallyidentical to mask pattern 20 is drawn inside mask pattern 19 as a maskpattern 21 by a broken line.

Thus a mask pattern dimensionally corrected by an amount varied betweenvertical and horizontal directions has allowed the peripheral circuitryportion to have a dense pattern also free of a difference betweenvertical and horizontal directions and hence as designed.

FIGS. 6A-6D show a mask pattern used to form an isolated pattern in theabove described flash memory at the peripheral circuitry portion. Notethat FIGS. 6A and 6B show a mask pattern used when unpolarized light isused to form the isolated pattern, and FIGS. 6C and 6D show a maskpattern used when linearly polarized light is used to form the isolatedpattern.

With reference to FIGS. 6A and 6B, L-shaped designed patterns 101, 102(indicated by broken line) extending in vertical (first) and horizontal(or second) directions, respectively, are geometrically identical.Designed patterns 101, 102 are formed through mask patterns 103, 104having main portions 105, 106 and projections 107, 108, and inner serifs109, 110 (first and second recesses) and serifs 111, 112 (first andsecond protrusions) inner and outer, respectively, than their respectivecorners. Note that as designed patterns 101, 102 are formed through anexposure process employing unpolarized light, designed patterns 101, 102are formed through geometrically identical mask patterns 103, 104.

With reference to FIGS. 6C and 6D, a wiring pattern formed by Spolarized light corresponds to a mask pattern 114 (a first maskpattern), which has a width (W1), and a wiring pattern formed by Ppolarized light corresponds to a mask pattern 113 (a second maskpattern), which has a width (W2) smaller than width W1. Note that inFIG. 6 a pattern geometrically identical to mask pattern 113 is drawninside mask pattern 114 by a broken line.

As shown in FIGS. 6C and 6D, horizontally and vertically extending maskpatterns 113 and 114, respectively, have their respective main portions115A and 115B different in width, their respective projections 116A and116B different in amount of projection, their respective inner serifportions 117A and 117B (the first and second recesses) different ingeometry, and their respective serif portions 118A and 118B (the firstand second protrusions) different in geometry. Vertically andhorizontally arranged and geometrically identical designed patterns canthus be formed.

Thus a mask pattern dimensionally corrected by an amount varied betweenvertical and horizontal directions has allowed an isolated pattern to bealso formed free of a difference between vertical and horizontaldirections and hence as designed. In contrast, when dimensionalcorrection was made without variation in amount and linearly polarizedlight was used to perform exposure to form vertical and horizontalpatterns, the patterns had a dimensional difference of approximately 3nm.

FIGS. 7A and 7B show a mask pattern used to form a straight-jointpattern in the above described flash memory at the peripheral circuitryportion.

With reference to the figures, the mask pattern for forming thestraight-joint pattern extending in the horizontal direction (seconddirection) has a main pattern 22 and a hammer head 23 and that forforming the straight-joint pattern extending in the vertical direction(first direction) has a main pattern 24 and a hammer head 25; Herein,main pattern 24 (the first mask pattern), corresponding to a wiringpattern formed by S polarized light, has a width (W1), and main pattern22 (the second mask pattern), corresponding to a wiring pattern formedby P polarized light, has a width (W2) smaller than width W1, and aswell the main patterns, hammer head 25 is increased in width to belarger than hammer head 23. Furthermore, hammer head 25 (the first maskpattern) is increased in thickness and has a spacing (W3) smaller than aspacing (W4) of hammer head 23 (or the second mask pattern).

Thus a mask pattern dimensionally corrected by an amount varied betweenvertical and horizontal directions has allowed the peripheral circuitryportion to have a straight-joint pattern also free of a differencebetween vertical and horizontal directions and hence as designed, andalso spaced by a small distance.

The present embodiment provides a semiconductor fabrication methodsummarized as follows:

In the present embodiment the semiconductor device fabrication method inone aspect is a method of fabricating a semiconductor device having afirst pattern (e.g., wiring pattern 14 in FIG. 3) extending in avertical direction (first direction), and a second pattern (e.g., wiringpattern 15 in FIG. 3) having a geometry identical to the first patternand extending in a horizontal direction (second direction) orthogonal tothe vertical direction, including the steps of: employing linearlypolarized illumination to provide exposure along a mask patternincluding a first mask pattern (e.g., mask pattern 16 in FIG. 4) and asecond mask pattern (e.g., mask pattern 17 in FIG. 4) for forming thefirst and second patterns, respectively; and subsequently forming thefirst and second patterns (e.g., wiring patterns 14 and 15 in FIG. 3)having a geometry in accordance with the mask pattern, the first andsecond mask patterns (e.g., mask patterns 16 and 17 in FIG. 4) beingformed to be different in geometry. As seen from a different point ofview, a mask pattern is dimensionally corrected by an amount variedbetween vertical and horizontal directions.

Furthermore, in another aspect, the above described first and secondmask patterns are different in width, while the first and secondpatterns have identical widths.

Herein if linear polarization has a vertical direction of polarization,the vertically extending mask pattern (first mask pattern) is increasedto be larger in width than the horizontally extending mask pattern(second mask pattern).

As one example of the first and second patterns, L-letter shapeddesigned patterns 101, 102 (the first and second patterns) areconsidered. Designed patterns 101, 102 correspond to mask patterns 113,114, which have corners 113A, 114A, and inner than corners 113A, 114A,inner serif portions 117A, 117B (the first and second recesses) areprovided, and outer than the corners serif portions 118A, 118B (thefirst and second protrusions) are provided. Mask patterns 113 and 114extending in vertical (first) and horizontal (second) directions,respectively, have their respective inner serifs 117A and 117B differentin geometry and their respective serifs 118A and 118B different ingeometry.

The first and second patterns may for example be a gate wiring pattern,a dense pattern, an isolated pattern, or, furthermore, a straight-jointpattern.

The present embodiment provides a semiconductor device including amemory cell portion and a peripheral circuitry portion. The abovedescribed concept may be implemented in either the memory cell portionor the peripheral circuitry portion.

In the present embodiment the above described concept allows a patternto be formed with reduced difference in dimension between vertical andhorizontal directions and hence as designed.

Second Embodiment

FIGS. 8A and 8B show a mask pattern used to form a wiring pattern in aflash memory (a semiconductor device) in a second embodiment.

With reference to the figures, a vertical main pattern 26 (first mainpattern) corresponding to a wiring pattern formed by S polarized lightand a horizontal main pattern 26A (second main pattern) corresponding toa wiring pattern formed by P polarized light are equal in width (W1). Itshould be noted, however, that horizontal main pattern 26A is sandwichedby a subpattern 27 (a dummy pattern) which is not resolved itself.

More specifically, the main patterns 26, 26A width (W1) is set to 240 nmon a mask, (60 nm as converted for a wafer). When subpattern 27 wasabsent, main patterns 26, 26A formed vertical and horizontal wiringpatterns with a difference in dimension of approximately 2 nm. Incontrast, when subpattern 27 was present on the mask, vertical andhorizontal wiring patterns were formed without a difference in dimensionas well as geometry. Note that subpattern 27 has a width (b1) ofapproximately 50 nm on the mask.

FIGS. 9A and 9B show an exemplary variation of the FIGS. 8A and 8B maskpatterns.

With reference to FIGS. 9A and 9B, a vertical main pattern 28 (firstmain pattern) corresponding to a wiring pattern formed by S polarizedlight and a horizontal main pattern 30 (second main pattern)corresponding to a wiring pattern formed by P polarized light are equalin width (W1). Furthermore, vertical main pattern 28 is sandwiched by asubpattern 29 which is not resolved itself, and horizontal main pattern26A is sandwiched by a subpattern 31 which is not resolved itself

More specifically, the main patterns 28, 30 have a width (W1) of 200 nmon a mask, (50 nm as converted for a wafer). Furthermore, subpattern 29has a width (b2) of approximately 35 nm on the mask and subpattern 31has a width (b3) of approximately 60 nm on the mask. Subpatterns 29, 31and main patterns 28, 30 are spaced equally between vertical andhorizontal directions. Vertical and horizontal wiring patterns can thusbe formed without a difference in dimension as well as geometry.

The present embodiment provides a semiconductor fabrication methodsummarized as follows:

In the present embodiment the semiconductor device fabrication method isa method of fabricating a semiconductor device having a wiring pattern(a first pattern) extending in a vertical direction (first direction),and a wiring pattern (a second pattern) having the same width as thefirst pattern and extending in a horizontal direction (second direction)orthogonal to the vertical direction, including the steps of: employinglinearly polarized light to transfer a mask pattern formed on a maskonto a resist film formed on a wafer; patterning the resist film; andusing the patterned resist mask to form a pattern, and the linearlypolarized light has a direction of polarization parallel to the verticaldirection (first direction) and to form the second pattern a maskpattern is provided that includes main pattern 26A corresponding to thesecond pattern and subpattern 27 sandwiching main pattern 26 and smallerin width than main pattern 26A (i.e., b 1<W1).

Main pattern 26A sandwiched by subpattern 27 allows a second patternextending in the horizontal direction (the direction of P polarization)to be formed with limited width. Consequently, the second pattern can bematched in width to the first pattern extending in the verticaldirection (the direction of S polarization), and a pattern can thus beformed with a limited difference in dimension between vertical andhorizontal directions and hence as designed.

Furthermore, main pattern 28 (the first main pattern) extendingvertically (in the direction of S polarization) that is sandwiched bysubpattern 29 (a first subpattern) and main pattern 30 (the second mainpattern) extending horizontally (in the direction of P polarization)that is sandwiched by subpattern 31 (a second subpattern), with thesubpattern 31 width (b3) greater than the subpattern 29 width (b2), canbe as effective as described above.

In the present invention, matters similar to those of the firstembodiment will not specifically be described.

Third Embodiment

FIGS. 10A and 10B are each a top view of a mask pattern employed to forma hole pattern on a wafer.

FIG. 10A shows a typical mask pattern. In the figure the mask patternincludes a halftone field portion 32 (a halftone region) and an opening33 having a square geometry. Exposing this mask pattern to unpolarizedlight forms a round hole pattern.

In contrast, FIG. 10B shows a layout of a mask pattern used in asemiconductor device fabrication method in accordance with the presentembodiment. In this figure, the mask pattern includes halftone fieldportion 32 (the halftone region) and an opening 34 having a rectangulargeometry with a vertical width (W2) (a first direction) greater than ahorizontal width (W1) (the second direction). Exposing this mask patternto vertically polarized light forms a round hole pattern. Note that inFIG. 10B the rectangle has a ratio between vertical and horizontaldimensions of approximately 1.6. This value, however, can be modifiedwithin a range of approximately 1.2 to 2. The ratio set within thisrange can ensure that abnormal transfer as described later cansufficiently be prevented, and can also prevent a hole pattern formedfrom having elliptical geometry. Note that light transmitted throughhalftone field portion 32 is adjusted to have a phase shifted by π ascompared with that transmitted through openings 34.

FIGS. 11A and 11B show a plurality of the FIGS. 10A and 10B maskpatterns arranged. In FIG. 11A a halftone field portion 40 has a squareopening 41 and in FIG. 11B halftone field portion 40 has a rectangularopening 42.

In the first embodiment a mask pattern in a direction (a firstdirection) in which linearly polarized light used for exposure providesS polarized illumination forms a line larger in width than that in adirection (a second direction) in which the linearly polarized lightprovides P polarized illumination to form a pattern free of a differencein dimension between vertical and horizontal directions. In the presentembodiment, an opening increased in width to be larger in the verticaldirection (or the first direction than the horizontal direction (thesecond direction) i.e., a halftone field portion is reduced in width tobe smaller in a direction in which linearly polarized light used forexposure provides S polarized illumination (i.e., the first direction)than a direction in which the linearly polarized light provides Ppolarized illumination (i.e., the second direction) to form a round holepattern. Thus the present embodiment provides a mask pattern having acharacteristic portion different from the first embodiment.

Thus in the present embodiment a dimensional correction opposite to thatin the first embodiment is introduced in order to prevent abnormallytransferring a sub peak serving as an obstacle to halftone exposure withimproved resolution. The sub peak indicates a spot having high opticalintensity caused in the vicinity of an opening by diffraction of lightfrom opening. As it interferes with light diffracted from a neighboringopening it increases in intensity and manifests as an abnormallytransferred image.

FIGS. 12A and 12B show patterns on a wafer that are formed through theFIGS. 11A and 11B mask patterns. Note that FIG. 12A shows a patternformed by exposing the FIG. 11A mask pattern to unpolarized light andFIG. 12B shows a pattern formed by exposing the FIG. 11B mask pattern tolinearly polarized light polarized in the vertical direction (firstdirection).

With reference to FIGS. 12A and 12B, a resist 43 has holes 44, 45 formedtherein. In FIG. 12A an abnormally transferred pattern 46 attributed tothe sub peak is formed between holes 44. In FIG. 12B, in contrast, thereis not an abnormal transfer attributed to a sub peak, since the exposureis performed with linearly polarized light and, as seen in its directionof polarization, the opening is relatively increased in width to provideexposure more efficiently and reduce the opening and field portion'srelative exposure ratio.

Note that while in the present embodiment the halftone field portion'stransmittance is set to approximately 6%, increasing the transmittancecan more effectively prevent abnormal transfer attributed to the subpeak. More specifically, the transmittance can be modified within arange of approximately 2% to 25%.

In the present embodiment a semiconductor device is fabricated in amethod summarized as follows:

In the present embodiment the semiconductor device fabrication method isa method of fabricating a semiconductor device having hole 45 (a holepattern) and includes the steps of: employing linearly polarized lightto transfer a mask pattern formed on a mask and including opening 42onto resist 43 deposited on a wafer; patterning resist 43; and using thepatterned resist 43 to form a pattern, and to form hole 45 opening 42 isprovided to have a width (W2) in a vertical direction (first direction)parallel to that of polarization of linearly polarized light larger thana width (W1) in a horizontal direction (second direction) orthogonal tothe vertical direction.

This can contribute to a limited abnormally transferred pattern formedon the resist that is attributed to the sub peak.

In the present embodiment, matters similar to those of the first andsecond embodiments will not specifically be described.

Fourth Embodiment

FIGS. 13A-13D are cross sections of resist patterns 51, 52, 51A, 52Aformed on a substrate 50 in a semiconductor device fabrication method inaccordance with a fourth embodiment. FIGS. 14A and 14B are top views ofthe resist patterns. FIGS. 13A and 13C show a cross section taken alonga line A-A in FIG. 14A and FIGS. 13B and 13D show a cross section takenalong a line B-B in FIG. 14B.

The FIGS. 13A-13D, and 14A and 14B resist patterns are used to form aline and space pattern having a width of approximately 70 nm. Thisresist pattern is formed for example with an exposure wavelength of 193nm and an NA of 0.92 applied as conditions for exposure.

FIGS. 13A and 13B show resist patterns 51, 52 formed when linearlypolarized light is used to perform exposure. Note that the linearlypolarized light's direction of polarization is a vertical direction inFIGS. 14A and 14B. More specifically, the FIG. 13A resist pattern 51 isformed by S polarized light and the FIG. 13B resist pattern 52 is formedby P polarized light.

With reference to FIGS. 13A and 13B, resist pattern 51 formed by Spolarized light tapers in cross section, whereas resist pattern 52formed by P polarized light is rectangular in cross section.

FIGS. 13C and 13D show resist patterns 51A, 52B formed when linearlypolarized light (first linearly polarized light) polarized vertically(in the first direction) and another linearly polarized light (secondlinearly polarized light) polarized horizontally (in the seconddirection) combined together are used to perform exposure. Note that thefirst linearly polarized light's direction of polarization is thevertical direction in FIGS. 14A and 14B and the second linearlypolarized light's direction of polarization is the horizontal directionin the same figures. Furthermore, the second linearly polarized lighthas an amplitude of approximately 5% of that of the first linearlypolarized light.

With reference to FIG. 13C, exposing to S polarized light and Ppolarized light combined together has allowed resist pattern 51A to beformed in a rectangle. Herein it can be ensured that resist pattern 51Ais substantially equivalent in resolution to resist pattern 51. Notethat resist pattern 52A is geometrically identical to resist pattern 52.Consequently, vertical/horizontal resist patterns' (51A, 52A) differencein dimension as well as geometry can be reduced.

Herein the first linearly polarized light and the second linearlypolarized light may be combined together by compositing them to provideelliptically polarized light for exposure or separately directing themfor exposure. More specifically, combining the first linearly polarizedlight and the second linearly polarized light together is a conceptincluding compositing them to provide elliptically polarized light andseparately directing them for exposure. The former allows exposure tocomplete at a time and thus provides increased throughput. The latterallows an optical system for exposure to be configured by a simpledevice and thus provides a more controllable polarization ratio (i.e., amore controllable ratio in amplitude between the first linearlypolarized light and the second linearly polarized light).

Furthermore in the present embodiment the second linearly polarizedlight is set to have an amplitude of 5% of that of the first linearlypolarized light. This value, however, can be modified within a range ofapproximately 2% to 20% (more preferably approximately 3% to 10%). Thefirst linearly polarized light and second linearly polarized lighthaving their respective amplitudes at a ratio set within this range canensure that a resist pattern has sufficient resolution and also preventS polarized light from transferring and forming a resist patterntapering as seen in cross section.

The present embodiment provides a semiconductor fabrication methodsummarized as follows:

The method employs an illumination device, a mask and a projective lensand includes the step of employing the device's illumination light totransfer a mask pattern formed on a mask onto a resist film formed on awafer, the illumination light being S polarized light (first polarizedlight) polarized in a vertical direction (first direction) parallel to adirection in which the mask pattern extends and P polarized light(second polarized light) polarized in a horizontal direction (seconddirection) orthogonal to the vertical direction combined together.

In the present invention, matters similar to those of the first to thirdembodiments will not specifically be described.

Thus the present invention's embodiments described above may have theirrespective, above described characteristic features combined asappropriate.

Although the present invention has been described and illustrated indetail, it is clearly understood that the same is by way of illustrationand example only and is not to be taken by way of limitation, the spiritand scope of the present invention being limited only by the terms ofthe appended claims.

INDUSTRIAL APPLICABILITY

Thus the present invention is applicable to semiconductor fabricationmethods and mask pattern data generation methods.

1. A method of fabricating a semiconductor device, including a firstpattern extending in a first direction and a second pattern identical ingeometry to said first pattern and extending in a second directionorthogonal to said first direction, comprising the steps of: employinglinearly polarized illumination to perform exposure along a mask patternincluding a first mask pattern and a second mask pattern used to formsaid first pattern and said second pattern, respectively; andsubsequently forming said first and second patterns having a geometryalong said mask pattern, said first and second mask patterns beingdifferent in geometry.
 2. The method of fabricating a semiconductordevice according to claim 1, wherein: said first direction is parallelto a direction of polarization of light passing through said first andsecond mask patterns for exposure; and said first mask pattern is largerin width than said second mask pattern.
 3. The method of fabricating asemiconductor device according to claim 1, wherein said first and secondmask patterns have first and second corners having first and secondrecesses different in geometry.
 4. The method of fabricating asemiconductor device according to claim 1, wherein said first and secondmask patterns have first and second corners having first and secondprotrusions different in geometry.
 5. A method of fabricating asemiconductor device including a first pattern extending in a firstdirection and a second pattern equal in width to said first pattern andextending in a second direction orthogonal to said first direction,comprising the steps of: employing linearly polarized illumination toperform exposure along a mask pattern including a first mask pattern anda second mask pattern used to form said first pattern and said secondpattern, respectively; and subsequently forming said first and secondpatterns having a geometry along said mask pattern, said first andsecond mask patterns being different in width.
 6. The method offabricating a semiconductor device according to claim 5, wherein: saidfirst direction is parallel to a direction of polarization of lightpassing through said first and second mask patterns for exposure; andsaid first mask pattern is larger in width than said second maskpattern.
 7. The method of fabricating a semiconductor device accordingto claim 5, wherein said first and second mask patterns have first andsecond corners having first and second recesses different in geometry.8. The method of fabricating a semiconductor device according to claim5, wherein said first and second mask patterns have first and secondcorners having first and second protrusions different in geometry.
 9. Amethod of fabricating a semiconductor device including a first isolatedpattern extending in a first direction and a second isolated patternidentical in geometry to said first isolated pattern and extending in asecond direction orthogonal to said first direction, comprising thesteps of: employing linearly polarized illumination to perform exposurealong a mask pattern including a first mask pattern and a second maskpattern used to form said first isolated pattern and said secondisolated pattern, respectively; and subsequently forming said first andsecond isolated patterns having a geometry along said mask pattern, saidfirst and second mask patterns being different in geometry.
 10. A methodof fabricating a semiconductor device including a memory cell portionand a peripheral circuitry portion, comprising the steps of: employinglinearly polarized light to transfer on a resist film formed on a wafera mask pattern formed on a mask; patterning said resist film; andemploying said resist film patterned to form a pattern, wherein to forma pattern of said peripheral circuitry portion said mask pattern isdimensionally corrected by an amount varied between vertical andhorizontal directions.
 11. A method of fabricating a semiconductordevice including a first pattern extending in a first direction and asecond pattern equal in width to said first pattern and extending in asecond direction orthogonal to said first direction, comprising thesteps of: employing linearly polarized light to transfer on a resistfilm formed on a wafer a mask pattern formed on a mask; patterning saidresist film; and employing said resist film patterned to form a pattern,wherein: said first direction is parallel to said linearly polarizedlight's direction of polarization; and to form said second pattern amask pattern is provided including a main pattern corresponding to saidsecond pattern and a subpattern smaller in width than said main patternand sandwiching said main pattern.
 12. A method of fabricating asemiconductor device including a first pattern extending in a firstdirection and a second pattern equal in width to said first pattern andextending in a second direction orthogonal to said first direction,comprising the steps of: employing linearly polarized light to transferon a resist film formed on a wafer a mask pattern formed on a mask;patterning said resist film; and employing said resist film patterned toform a pattern, wherein: to form said first pattern a first mask patternis provided including a first main pattern corresponding to said firstpattern and a first subpattern smaller in width than said first mainpattern and sandwiching said first main pattern; to form said secondpattern a second mask pattern is provided including a second mainpattern corresponding to said second pattern and a second subpatternsmaller in width than said second main pattern and sandwiching saidsecond main pattern; and said second subpattern is larger in width thansaid first subpattern.
 13. A method of fabricating a semiconductordevice including a hole pattern, comprising the steps of: employinglinearly polarized light to transfer on a resist film formed on a wafera mask pattern formed on a mask; patterning said resist film; andemploying said resist film patterned to form a pattern, wherein to formsaid hole pattern said mask pattern has an opening larger in width in afirst direction parallel to said linearly polarized light's direction ofpolarization than a second direction orthogonal to said first direction.14. The method of fabricating a semiconductor device according to claim13, wherein said mask pattern has a halftone region.
 15. A method offabricating a semiconductor device, employing an illumination device, amask and a projective lens, comprising the step of employing saidillumination device 's illumination light to transfer on a resist filmformed on a wafer a mask pattern formed on a mask, wherein saidillumination light is first linearly polarized light and second linearlypolarized light combined together, said first linearly polarized lighthaving a direction of polarization in a first direction parallel to adirection of extension of said mask pattern, second linearly polarizedlight having a direction of polarization in a second directionorthogonal to said first direction.
 16. The method of fabricating asemiconductor device according to claim 15, wherein said second linearlypolarized light has an amplitude of 2 to 20% of that of said firstlinearly polarized light.
 17. A method of generating mask pattern datadefining a mask pattern for forming a pattern on a wafer by linearlypolarized light, the method introducing a dimensional correction by anamount varied between a first direction parallel to said linearlypolarized light's direction of polarization and a second directionorthogonal to said first direction.